Recent tests performed on the D-Wave Two quantum annealer have revealed noclear evidence of speedup over conventional silicon-based technologies. Here,we present results from classical parallel-tempering Monte Carlo simulationscombined with isoenergetic cluster moves of the archetypal benchmark problem-anIsing spin glass-on the native chip topology. Using realistic uncorrelatednoise models for the D-Wave Two quantum annealer, we study the best-caseresilience, i.e., the probability that the ground-state configuration is notaffected by random fields and random-bond fluctuations found on the chip. Wethus compute classical upper-bound success probabilities for different types ofdisorder used in the benchmarks and predict that an increase in the number ofqubits will require either error correction schemes or a drastic reduction ofthe intrinsic noise found in these devices. We outline strategies to developrobust, as well as hard benchmarks for quantum annealing devices, as well asany other computing paradigm affected by noise.
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